In many types of static power conversion equipment, such as static VAR generators (SVG's), the controllability of the required output relies on the availability of synchronous timing signals. The synchronous timing signals are used, generally, as firing angle references for switching or phase control. In SVG's that essentially consist of thyristor controlled reactors and thyristor switched capacitors, the timing signals are derived from the voltage of electric power transmission lines. An example of an SVG control with reference to timing signals is described in U.S. Pat. No. 3,999,117, issued Dec. 21, 1976 and entitled "Control Apparatus for Static VAR Generators and ARC Furnace Flicker Compensators". A timing reference generator for arc furnace flicker compensators is described in U.S. Pat. No. 3,987,360 issued Oct. 19, 1976 entitled "High Accuracy Fast Recovery Reference Timing Generator for a Static VAR Generator". The synchronous timing signals are, essentially, digital pulses that are locked in prescribed and steady phase relationships with the transmission line voltage signals. When, after start-up, the phase relationships are established, that is the timing reference generator has "captured" or locked onto the transmission line voltage signals, the phase of the output signals will track within specified rate of change of frequency variations of the electric power network. The maximum phase error during tracking must also stay within prescribed limits.
One of the most critical timing requirements is faced in power utility type SVG's. A major function of utility type SVG's is to preserve power system stability after inadvertent line faults (short circuits). During a line fault, the voltage may completely disappear or may become grossly distorted for several line voltage periods, typically 3-6 cycles. The SVG cannot regulate the system during a fault due to the lack of system voltage or excessive voltage unbalance. However, it is extremely important that after the fault has cleared, the SVG resumes its control of the transmission network as soon as possible.
As described in U.S. Pat. No. 3,987,360, a timing reference generator can be based on a phase-locked type circuit. Typically the phase-locked loop circuit is comprised of a phase detector, a loop filter or integrator, and a voltage controlled oscillator (VCO) whose output is the timing reference signal. The output of the VCO and the line voltage signal serve as the input to the phase detector. The phase-locked loop is designed so that the timing reference signal output will lock onto and track the line voltage signal in a predetermined phase relationship. There are certain operational advantages if the generation of timing references is based on the fundamental (60 Hz) positive sequence component of the measured, multi-phase system voltages. A positive sequence based timing reference generator can be implemented by a positive sequence locked loop described in the cross referenced application. The positive sequence locked loop described there also employs phase locked loop techniques. A high accuracy timing reference can be made using this circuit by inserting band reject filters in the positive sequence locked loop. This circuit would be accurate even in the case of system voltage unbalance and (second) harmonic content. For example, the insertion of a second harmonic band reject filter eliminates the significant phase errors caused by even a typically small amount (2%) of steady state voltage unbalance. An additional series third harmonic band reject filter will eliminate phase errors caused by the presence of balanced second harmonics also. A third fundamental (60 Hz) band reject filter eliminates the effect of unbalanced second harmonics and dc offset in the input signals. A large amount of second harmonic content is generally observed right after clearing of faults.
Unfortunately, even the above, improved positive sequence locked loop cannot override severe line faults when practically all of the line voltages disappear. The phase locked loop tends to interpret the disappearance of the voltage as a large phase error (one approaching 180 degrees) and quickly but also incorrectly alters the phase of the synchronous output signals. During the fault, the synchronism is lost and, in worst case, a full signal recapture, i.e. starting from an initial phase error of 180 degrees, and output settling will be required from the phase locked loop. This also means that there is no usable timing reference immediately after fault clearance when it is needed the most for fast corrective action by the SVG.
In order to preserve its prefault phase position, the normal closed phase locked loop (PLL) could, theoretically, be opened before the phase detector affects the loop filter and, eventually, the voltage controlled oscillator (VCO) that provides the timing references. This can be implemented by placing a switch in the signal line between the phase detector and the loop filter. Normally, the disconnect switch is closed (ON). This allows capturing and tracking the input voltage. When the input and output signals are in phase, the phase detector output is zero (open circuit). For lagging and leading phase errors, the phase detector injects a respective proportional positive or negative charge into the loop filter. For example, when the phase of the output signal lags the input phase, the frequency of the VCO will increase and, consequently, its output phase will advance in time. Similarly, by appropriate modification of the VCO frequency, the loop can correct for phase leads. When the loop is settled, the output of the phase detector becomes zero. The switch can now be opened and only a very small phase drift is observed at the VCO output due to small circuit leakages. The PLL behaves as a mechanical "flywheel" with very high inertia.
The problem with this "flywheel" technique arises in providing the disconnect signal to the switch in time before the output phase becomes altered by the unpredictable beginning of the fault. The problem is due to the fact that the sensing time of the fault occurrence is comparable to the combined phase detector and loop filter time constant. The activation delay of the disconnect switch becomes less pronounced if the loop filter time constant is increased. Above a certain time constant, oscillatory tendency is observed in the SVG operation. The oscillatory tendency diminishes with further increase of the time constant, but at this point the PLL response becomes so slow that it cannot follow the specified rate of change of system frequencies with an acceptable phase error. No acceptable compromise can be found to obtain a high quality fault tolerant timing reference generator based on the simple flywheel technique described.
One subject of the present invention is to provide a line fault tolerant synchronous multiphase timing reference. Another object of the invention is to provide a multiphase timing reference circuit capable of withstanding a multiple line fault condition.